 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CXD3017Q CD Digital Signal Processor with Built-in Digital Servo and DAC Description The CXD3017Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter. Features Digital Signal Processor (DSP) Block * 1x, 2x, 4x speed playback supported * 16K-RAM * EFM data demodulation * Enhanced EFM frame sync signal protection * SEC strategy-based error correction * Subcode demodulation and Sub Q data error detection * Digital spindle servo * 16-bit traverse counter * Asymmetry compensation circuit * CPU interface on serial bus * Error correction monitor signal, etc. output from a new CPU interface * Servo auto sequencer * Digital audio interface outputs * Digital level meter, peak meter * CD TEXT data demodulation Digital Servo (DSSP) Block * Microcomputer software-based flexible servo control * Offset cancel function for servo error signal * Auto gain control function for servo loop * E:F balance, focus bias adjustment function * Surf jump function supporting micro two-axis * Tracking filter: 6 stages, focus filter: 5 stages Digital Filter, DAC and Analog Low-pass Filter Blocks * DBB (digital bass boost) function * Double-speed playback supported * Digital de-emphasis * Digital attenuation * 8Fs oversampling filter Applications CD players 80 pin LQFP (Plastic) Structure Silicon gate CMOS IC Absolute Maximum Ratings * Supply voltage VDD -0.5 to +4.6 V * Input voltage VI -0.5 to +4.6 V (VSS - 0.5V to VDD + 0.5V) * Output voltage VO -0.5 to +4.6 V (VSS - 0.5V to VDD + 0.5V) * Storage temperature Tstg -55 to +150 C * Supply voltage difference VSS - AVSS -0.3 to +0.3 V VDD - AVDD -0.3 to +0.3 V Note) AVDD includes XVDD and AVSS includes XVSS. Recommended Operating Conditions * Supply voltage VDD 2.7 to 3.6 * Operating temperature Topr -20 to +75 Playback speed 4x 2x 1x VDD [V] CD-DSP block 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 pF pF pF DAC block V C I/O Capacitance 9 (Max.) * Input pin CI * Output pin CO 11 (Max.) * I/O pin CI/O 11 (Max.) Note) Measurement conditions VDD = VI = 0V fM = 1MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E99Y24-PS CXD3017Q Block Diagram EMPH WFCK PCMD XUGF BCK SYSM C2PO XTSL GFS LRCK DAC Block TES1 TEST Clock Generator RFAC ASYI ASYO BIAS XPCK FILO FILI PCO CLTV MDP LOCK SENS DATA XLAT CLOK SPOA SPOB XLON SCOR SQSO SQCK Signal Processor Block Servo Block CPU Interface Servo Auto Sequencer Digital CLV Digital PLL Sub Code Processor Asymmetry Corrector EFM demodurator Error Corrector D/A Interface Serial-In Interface Over Sampling Digital Filter 16K RAM Digital OUT Timing Logic XRST RMUT LMUT XTAI XTAO 3rd-Order Noise Shaper PWM PWM AOUT1 AIN1 LOUT1 AOUT2 AIN2 LOUT2 DOUT SCLK SERVO Interface COUT SSTP ATSK MIRR DFCT FOK SERVO DSP PWM GENERATOR FOCUS PWM GENERATOR TRACKING PWM GENERATOR SLED PWM GENERATOR FFDR FRDR TFDR TRDR SFDR SRDR MIRR DFCT FOK RFDC CE TE SE FE VC IGEN OPAmp Analog SW A/D Converter FOCUS SERVO TRACKING SERVO SLED SERVO ADIO -2- CXD3017Q Pin Configuration AVDD3 AVDD0 DOUT AVSS3 RFAC ASYO AVSS0 FILI ASYI RFDC CLTV FILO VDD VSS IGEN PCO BIAS ADIO CE 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 LRCK 61 PCMD 62 BCK 63 EMPH 64 XVDD 65 XTAI 66 XTAO 67 XVSS 68 AVDD1 69 AOUT1 70 AIN1 71 LOUT1 72 AVSS1 73 AVSS2 74 LOUT2 75 AIN2 76 AOUT2 77 AVDD2 78 RMUT 79 LMUT 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 SE 39 FE 38 VC 37 XTSL 36 TES1 35 TEST 34 VSS 33 FRDR 32 FFDR 31 TRDR 30 TFDR 29 SRDR 28 SFDR 27 SSTP 26 MDP 25 LOCK 24 FOK 23 DFCT 22 MIRR 21 COUT SYSM WFCK XUGF XPCK DATA XRST SCLK ATSK VDD SQSO -3- SCOR SQCK SENS XLON SPOB CLOK SPOA C2PO XLAT GFS TE CXD3017Q Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol SQSO SQCK XRST SYSM DATA XLAT CLOK SENS SCLK VDD ATSK SPOA SPOB XLON WFCK XUGF XPCK GFS C2PO SCOR COUT MIRR DFCT FOK LOCK MDP SSTP SFDR SRDR TFDR TRDR FFDR FRDR VSS I/O O I I I I I I O I -- I/O I I O O O O O O O I/O I/O I/O I/O I/O O I O O O O O O -- 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 -- 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, Z, 0 -- 1, 0 1, 0 Output values 1, 0 Description Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data output. SQSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Digital power supply. Anti-shock input/output. Microcomputer extension interface (input A) Microcomputer extension interface (input B) Microcomputer extension interface (output) WFCK output. XUGF output. MINT1 or RFCK is output by switching with the command. XPCK output. MNT0 is output by switching with the command. GFS output. MNT3 or XROF is output by switching with the command. C2PO output. GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected. Track count signal input/output. Mirror signal input/output. Defect signal input/output. Focus OK signal input/output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1. Spindle motor servo control output. Disc innermost track detection signal input. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital GND. -4- CXD3017Q Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol TEST TES1 XTSL VC FE SE TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI BIAS RFAC AVSS3 CLTV FILO FILI PCO AVDD3 VSS VDD DOUT LRCK PCMD BCK EMPH XVDD XTAI XTAO XVSS I/O I I I I I I I I I O -- I -- O I I I -- I O I O -- -- -- O O O O O -- I O -- Output values Test pin. Normally, GND. Test pin. Normally, GND. Description Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Analog -- Test pin. No connected. Analog GND. Operational amplifier constant current input. -- 1, 0 Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Asymmetry comparator voltage input. Asymmetry circuit constant current input. EFM signal input. -- Analog GND. Multiplier VCO1 control voltage input. Analog Master PLL filter output. (slave = digital PLL) Master PLL filter input. 1, Z, 0 -- -- -- 1, 0 1, 0 1, 0 1, 0 1, 0 -- Master PLL charge pump output. Analog power supply. Digital GND. Digital power supply. Digital Out output. D/A interface. LR clock output f = Fs. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. -- Master clock GND. -5- CXD3017Q Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 Symbol AVDD1 AOUT1 AIN1 LOUT1 AVSS1 AVSS2 LOUT2 AIN2 AOUT2 AVDD2 RMUT LMUT I/O -- O I O -- -- O I O -- O O Output values -- Analog power supply. L ch analog output. L ch operational amplifier input. L ch LINE output. -- -- Analog GND. Analog GND. R ch LINE output. Description R ch operational amplifier output. R ch analog output. -- 1, 0 1, 0 Analog power supply. R ch zero detection flag. L ch zero detection flag. Notes) * PCMD is a MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) * XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. * XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136s. * C2PO represents the data error status. * XROF is generated when the 16K RAM exceeds the 4F jitter margin. Monitor Pin Output Combinations Command bit MTSL1 0 0 1 MTSL0 0 1 0 XUGF MNT1 RFCK Output data XPCK MNT0 XPCK GFS MNT3 XROF C2PO C2PO GTOP -6- CXD3017Q Electrical Characteristics 1. DC Characteristics Item Input voltage (1) High level Low level High level Low level High level Low level VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIN4 High level Low level High level Low level VOH1 VOL1 VOH2 VOL2 ILI1 ILI2 ILI3 ILI4 ILO VI 5.5V VI 5.5V Schmitt input Analog input IOH = -4mA IOL = 4mA 0.8VDD 0.2VDD 0.8VDD 0.2VDD VSS VDD - 0.4 0 VDD VDD 0.4 VDD 0.4 10 10 40 40 40 (VDD = AVDD = 3.3 0.3V, Vss = AVss = 0V, Topr = -20 to +75C) Conditions Min. 0.7VDD 0.2VDD Typ. Max. Unit V V V V V V V V V V V A A A A A Applicable pins 1, 9 2 3 4, 5 6, 8, 9 7 1, 4 2, 3 9 5 8 Input voltage (2) Input voltage (3) Input voltage (4) Output voltage (1) Output voltage (2) Input leak current (1) Input leak current (2) Input leak current (3) Input leak current (4) IOH = -0.28mA VDD - 0.5 IOH = 0.36mA 0 VI = Vss or VDD VI = 0 to 5.5V VI = Vss or VDD VI = 0.25VDD to 0.75VDD VI = Vss or VDD -10 -10 -40 -40 -40 Tri-state pin output leak current 1-1. Applicable pins and classification 1 CMOS level input pins (1): TEST, TES1 2 CMOS level input pins (2): SYSM, DATA, XLAT, SSTP, XTSL 3 CMOS Schmitt input pins: SQCK, XRST, CLOK, SCLK, SPOA, SPOB 4 Analog input pins (1): ASYI, CLTV, FILI 5 Analog input pins (2): VC, FE, SE, TE, CE, RFDC 6 Normal output pins (1): SQSO, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, SFDR, SRDR, TFDR, TRDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT 7 Normal output pin (2): FILO 8 Tri-state output pins: SENS, MDP, FFDR, PCO 9 Normal input/output pins: ATSK, COUT, MIRR, DFCT, FOK, LOCK Note) When the external pull-down resistors are connected to the pins 2 and 3, the resistance applied to these pins should be 5k or less in total. -7- CXD3017Q 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = -20 to +75C, VDD = AVDD = 3.3 0.3V) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz (b) When inputting pulses to XTAI pin (Topr = -20 to +75C, VDD = AVDD = 3.3 0.3V) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 0.7VDD 0.2VDD 10 Typ. Max. 500 500 1000 Unit ns ns ns V V ns tWHX tWLX tCX VIHX VILX tR, tF tCK tWHX tWLX VIHX VIHX x 0.9 XTAI VDD/2 VIHX x 0.1 VILX tR tF (c) When inputting sine waves to XTAI pin via a capacitor (Topr = -20 to +75C, VDD = AVDD = 3.3 0.3V) Item Input amplitude Symbol VI Min. 0.5VDD Typ. Max. unit VDD + 0.3 Vp-p -8- CXD3017Q (2) CLOK, DATA, XLAT and SQCK pin (VDD = AVDD = 3.3 0.3V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width SQCK frequency SQCK pulse width Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65 Note) 750 Note) Unit MHz ns ns ns ns ns MHz ns tWCK tSU tH tD tWL fT tWT 1/fCK tWCK tWCK CLOK DATA XLAT tSU SQCK tWT 1/fT SQSO tSU tH tWT tH tD tWL Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum operating frequency is 300kHz and its minimum pulse width is 1.5s. -9- CXD3017Q (3) SCLK pin XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) ... MSB ... LSB Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 Unit MHz ns s tSPW tDLS 31.3 15 (4) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 3.3 0.3V, VSS = AVSS = 0V, Topr = -20 to +75C) Item COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency Symbol Min. Typ. Max. Unit fCOUT fMIRR fDFCTH 40 40 5 kHz kHz kHz Conditions 1 2 3 1 When using a high-speed traverse TZC. 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. * A = 0.11VDD to 0.23VDD * B 25% A+B 3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. - 10 - CXD3017Q 1-bit DAC and LPF Block Analog Characteristics Analog characteristics (VDD = AVDD = 3.3V, VSS = AVSS = 0V, Ta = 25C) Item Total harmonic distortion Signal-to-noise ratio Symbol THD Conditions 1kHz, 0dB data 1kHz, 0dB data when AMUT ON (Using A-weighting filter) Crystal 384Fs 768Fs 384Fs 768Fs 98 98 Min. Typ. 0.0080 0.0080 102 102 Max. 0.0120 0.0120 dB Unit % S/N Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. Note) The external load capacitance connect to the LPF block should be 30pF or less in total. 27k AOUT1 (2) 330pF 27k AIN1 (2) 68pF LOUT1 (2) 22 100k Audio Analyzer 27k SHIBASOKU (AM51A) LPF external circuit diagram 768Fs/384Fs Rch DATA TEST DISC RF CXD3017Q Lch A Audio Analyzer B Block diagram of analog characteristics measurement (VDD = AVDD = 3.3V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Output voltage Load resistance Load capacitance Symbol VOUT RL CL 20 30 Min. Typ. 0.71 Max. Unit Vrms k pF Applicable pins 1 1 1, 2 Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB. Applicable pins 1 LOUT1, LOUT2 2 AOUT1, AOUT2 - 11 - CXD3017Q Contents 1. CPU Interface 1-1. CPU Interface Timing ........................................................................................................................ 13 1-2. CPU Interface Command Table ........................................................................................................ 13 1-3. CPU Command Presets .................................................................................................................... 24 1-4. Description of SENS Signals and Commands ................................................................................... 30 2. Subcode Interface 2-1. 80-bit Sub Q Readout ........................................................................................................................ 46 3. Description of Other Functions 3-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 49 3-2. Frame Sync Protection ...................................................................................................................... 50 3-3. Error Correction ................................................................................................................................. 50 3-4. DA Interface ....................................................................................................................................... 51 3-5. Digital Out .......................................................................................................................................... 53 3-6. Servo Auto Sequence ....................................................................................................................... 53 3-7. Digital CLV ......................................................................................................................................... 60 3-8. CD-DSP Block Playback Speed ........................................................................................................ 61 3-9. DAC Block Playback Speed .............................................................................................................. 61 3-10. Description of DAC Block Functions .................................................................................................. 62 3-11. LPF Block .......................................................................................................................................... 65 3-12. Asymmetry Compensation ................................................................................................................ 66 3-13. CD TEXT Data Demodulation ........................................................................................................... 67 4. Description of Servo Signal Processing System Functions and Commands 4-1. General Description of Servo Signal Processing System .................................................................. 69 4-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 70 4-3. DC Offset Cancel [AVRG Measurement and Compensation] ........................................................... 71 4-4. E:F Balance Adjustment Function ..................................................................................................... 72 4-5. FCS Bias Adjustment Function .......................................................................................................... 72 4-6. AGCNTL Function ............................................................................................................................. 74 4-7. FCS Servo and FCS Search ............................................................................................................. 76 4-8. TRK and SLD Servo Control ............................................................................................................. 77 4-9. MIRR and DFCT Signal Generation .................................................................................................. 78 4-10. DFCT Countermeasure Circuit .......................................................................................................... 79 4-11. Anti-Shock Circuit .............................................................................................................................. 79 4-12. Brake Circuit ...................................................................................................................................... 80 4-13. COUT Signal ..................................................................................................................................... 81 4-14. Serial Readout Circuit ........................................................................................................................ 81 4-15. Writing to the Coefficient RAM .......................................................................................................... 82 4-16. PWM Output ...................................................................................................................................... 82 4-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 83 4-18. Description of Commands and Data Sets ......................................................................................... 83 4-19. List of Servo Filter Coefficients ........................................................................................................ 107 4-20. Filter Composition ............................................................................................................................ 109 4-21. TRACKING and FOCUS Frequency Response .............................................................................. 115 5. Application Circuit .................................................................................................................................. 116 Explanation of abbreviations AVRG: AGCNTL: FCS: TRK: SLD: DFCT: Average Auto gain control Focus Tracking Sled Defect - 12 - CXD3017Q 1. CPU Interface 1-1. CPU Interface Timing * CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D0 D1 D18 D19 D20 D21 D22 D23 750ns or more XLAT Registers Valid * The internal registers are initialized by a reset when XRST = 0. Note) Be sure to set SQCK to high when XLAT is low. 1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 4 to 6 7 8 9 A B C D E Total bit length 8 bits 8 to 24 bits 8 bits 20 bits 28 bits 24 bits 28 bits 16 bits 8 bits 16 bits 20 bits - 13 - Command Table ($0X to 1X) Data 1 D17 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT -- -- FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SEARCH VOLTAGE DOWN -- FOCUS SEACH VOLTAGE UP -- ANTI SHOCK ON -- ANTI SHOCK OFF -- BRAKE ON -- BRAKE OFF -- TRACKING GAIN NORMAL -- TRACKING GAIN UP -- TRACKING GAIN UP FILTER SELECT 1 -- -- -- TRACKING GAIN UP FILTER SELECT 2 -- --: Don't care CXD3017Q Data 2 Data 3 Data 4 Data 5 Address Register Command D23 to D20 D19 0 D18 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 FOCUS CONTROL 0000 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 1 0 -- -- -- -- -- -- 1 0 -- -- -- -- 1 -- 1 0 - 14 - 1 0 -- -- 1 TRACKING CONTROL 0001 -- -- -- -- Command Table ($2X to 3X) Data 1 D18 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 5 D6 -- -- -- -- -- -- -- -- -- -- -- D5 -- -- -- -- D4 -- -- -- -- D3 -- -- -- -- D2 -- -- -- -- D1 -- -- -- -- D0 -- -- -- -- SLED KICK LEVEL (1 x basic value) (Default) -- -- -- SLED KICK LEVEL (2 x basic value) -- -- SLED KICK LEVEL (3 x basic value) -- SLED KICK LEVEL (4 x basic value) -- --: Don't care -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 4 D8 D7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 3 D12 -- -- -- -- -- -- -- -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 -- -- -- -- -- -- -- -- -- -- -- -- D14 D13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 1 -- -- -- -- Data 1 D18 0 0 0 0 1 1 1 0 0 1 0 0 D17 D16 1 1 1 0 0 1 0 0 -- -- -- -- -- -- -- -- D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE D6 D5 D4 Data 2 Data 3 Data 4 Data 5 Address Register Command D23 to D20 D19 0 0 1 1 2 TRACKING MODE 0010 -- -- -- - 15 - -- Address Register Command D23 to D20 D19 0 0 3 SELECT 0011 0 0 CXD3017Q Command Table ($340X) Address 3 D10 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K01) SLED LOW BOOST FILTER A-H KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN 1 CXD3017Q 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 KRAM DATA (K00) SLED INPUT GAIN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0000 1 1 1 1 1 1 1 1 - 16 - 3 SELECT 0011 0100 Command Table ($341X) Address 3 D10 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L 1 CXD3017Q 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K12) ANTI SHOCK INPUT GAIN 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K11) FOCUS OUTPUT GAIN 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0001 1 1 1 1 1 1 1 1 - 17 - 3 SELECT 0011 0100 Command Table ($342X) Address 3 D10 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2E) Not used KRAM DATA (K2F) Not used 1 CXD3017Q 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K22) TRACKING OUTPUT GAIN 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0010 1 1 1 1 1 1 1 1 - 18 - 3 SELECT 0011 0100 Command Table ($343X) Address 3 D10 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K32) Not used KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3F) Not used 1 CXD3017Q 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 KRAM DATA (K30) SLED INPUT GAIN (when SFSK = 1 TG up2) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0011 1 1 1 1 1 1 1 1 - 19 - 3 SELECT 0011 0100 Command Table ($344X) Address 3 D10 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K42) TRACKING HOLD FILTER A-L KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2) KRAM DATA (K47) Not used KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) Not used KRAM DATA (K4F) Not used 1 CXD3017Q 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K41) TRACKING HOLD FILTER A-H 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address 4 Data 1 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 0100 1 1 1 1 1 1 1 1 - 20 - 3 SELECT 0011 0100 Command Table ($348X to 34FX) Address 3 Data 1 Data 2 D8 D7 0 0 PFOK, RFAC Booster Surf Brake 0 0 0 0 0 0 0 Data 3 D4 D3 D2 D1 D0 -- -- TV2 TV1 TV3 TV0 FCS Bias Limit FCS Bias Data FB2 FB1 Traverse Center Data Data 2 D7 D6 D5 IDFT1 IDFT0 0 0 INVRFDC DFCT HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 Booster 0 0 0 0 0 0 MRS MRT1 MRT0 0 D6 D5 D4 D3 D2 D1 D0 Data 3 D12 D11 0 0 PFOK1 PFOK0 0 0 SFBK1 SFBK2 THBON FHBON TLB10N FLB1ON TLB2ON IDFS3 IDFS2 IDFS1 IDFS0 0 Data 1 D11 1 0 1 FB9 TV9 TV8 TV7 TV5 TV4 TV6 FB3 0 FB8 FB7 FB5 FB4 FB6 1 0 1 1 0 1 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 D10 D9 D8 D10 D9 0 1 0 0 D14 0 0 1 1 Address 3 D15 D14 D13 D12 1 0 1 0 D13 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 1 1 1 1 3 SELECT 0011 0100 - 21 - CXD3017Q Command Table ($35X to 3FX) Address 2 D17 1 Data 1 D17 0 1 0 TJ1 1 0 1 0 0 0 0 0 1 0 0 1 0 1 0 SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 FBON 0 0 0 FI FZC DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 DTZC TJ5 TJ4 TJ3 TJ2 FT1 FS2 FS1 FS0 1 1 0 0 1 1 0 0 1 1 FT0 FS5 FS4 FS3 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE/AUTO GAIN DTZC/TRACK JUMP VOLTAGE/AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) 0 0 0 0 0 0 0 0 0 0 ASFG FTQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SERIAL DATA READ MODE/SELECT FOCUS BIAS Operation for MIRR/ DFCT/FOK TZC/COUT BOTTOM/MIRR BTS1 BTS0 MRC1 MRC0 SLED FILTER LKIN COIN MDFI MIRI XT1D Filter 1 SRO1 0 AGHF ASOT Others --: Don't care Data 2 Data 3 Data 4 1 1 0 0 SYG3 SYG2 SYG1 SYG0 0 FI FI FI FI FI FI FI FI System GAIN FZB3 FZB2 FZB1 FZB0 FZA3 FZA2 FZA1 FZA0 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Data 3 Address 1 Register Command D23 to D20 D19 1 D18 0011 1 Address D23 to D20 D19 1 1 1 0 0 0 0 1 1 1 1 D18 0 0 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 1 3 SELECT 1 - 22 - F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD AGG4 XT4D XT2D AGSD DRR2 DRR1 DRR0 0011 1 FPS1 FPS0 TPS1 TPS0 SVDA 1 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 1 1 1 1 CXD3017Q Instruction Table Data 1 Data 3 Data 4 D0 D3 -- -- -- -- -- -- -- -- -- -- D2 D1 D0 -- D3 D2 D1 D0 D3 D2 D1 -- D0 -- -- -- -- D3 D2 D1 Data 5 Data 6 D0 -- D0 D3 -- -- -- D2 D1 0 0.18ms 0.09ms 0.05ms 0.02ms -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.36ms 0.18ms 0.09ms 0.05ms 0 -- 11.6ms 5.8ms 2.9ms 1.45ms -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AS3 AS2 AS1 AS0 D3 D2 D1 D0 Data 2 Address Register Command D3 D2 D1 4 Auto sequence 0 1 0 5 1 Blind (A, E), Overflow (C) Brake (B) 0 1 0 -- -- -- -- 6 Kick (D) 0 1 1 7 1 32768 16384 8192 4096 2048 1024 512 128 64 32 16 8 4 2 1 -- 256 Auto sequence (N) track jump count 0 CDROM 0 SOCT 1 0 0 VCO DOUT DOUT WSEL SEL1 Mute ON/OFF 0 KSL3 KSL2 0 0 VCO1 CS0 -- DSPB ON/OFF 0 0 0 0 0 0 0 0 DSPB ON/OFF 0 0 0 0 0 0 0 0 0 Mute ATT 0 0 OPSL1 MCSL 1 ZDPL ZMUT OPSL1 MCSL 0 ZDPL ZMUT -- 0 0 1 1 -- -- -- -- -- -- -- 8 Mode specification 1 0 1 0 0 0 0 0 TXON TXOUT OUTL1 OUTL0 1 0 0 -- -- -- -- -- -- -- -- 9 1 0 Function specification - 23 - 0 0 0 0 0 0 Mute ATT 0 0 1 1 0 0 1 ADCPS DSP DSSP ASYM SLEEP SLEEP SLEEP 0 LPF SLEEP 0 0 0 -- 1 SL1 SL0 CPUSR 0 TRMI TRMO MTSL1 MTSL0 0 0 -- 0 Gain Gain Gain Gain -- MDP1 MDP0 MDS1 MDS0 -- 0 TB TP Gain CLVS 1 0 1 -- -- -- -- -- -- -- 1 1 0 0 0 0 0 -- 0 CM3 CM2 CM1 CM0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 DCOF 0 DAC -- PWDN -- -- -- -- 1 0 1 OPSL2 EMPH SMUT AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 -- -- -- A Audio CTRL OPSL2 EMPH SMUT AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT LRWO BSBST BBSL 1 -- -- -- -- -- -- -- -- -- -- -- 1 0 1 A Sleep setting 1 0 1 B Serial bus CTRL 1 0 1 -- -- -- -- -- -- -- -- -- -- -- C Spindle servo coefficient setting 1 1 0 -- -- -- -- -- -- -- -- -- -- -- D CLV CTRL 1 1 0 -- -- -- -- -- -- -- -- -- -- -- CXD3017Q E CLV mode 1 1 1 0 0 0 -- -- -- -- -- -- -- -- 1-3. CPU Command Presets Command Preset Table ($0X to 34X) Data 1 D18 0 0 -- -- -- -- -- -- Data 5 D4 -- -- D3 D2 -- D0 -- Data 2 D4 D3 D5 D2 D0 D0 KRAM DATA ($3400XX to $344fXX) --: Don't care D0 -- SLED KICK LEVEL (1 x basic value) (Default) -- -- -- -- -- -- -- -- -- -- -- Data 4 D8 -- Data 1 D8 D7 D6 -- -- -- D7 D6 D5 -- -- -- -- -- -- -- -- Data 3 D12 -- Address 3 D12 D11 D10 D9 -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 Data 1 D18 0 Address 2 D17 0 0 0 D16 D15 D14 D13 0 0 -- -- -- D17 D16 D15 D14 D13 Data 2 0 -- -- 1 -- -- 0 -- -- 0 0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF Data 2 Data 3 Data 4 Data 5 Address Register Command D23 to D20 D19 0 FOCUS CONTROL 0000 0 1 TRACKING CONTROL 0001 0 2 TRACKING MODE 0010 0 Address Register Command D23 to D20 D19 0011 0 Address 1 D18 1 3 SELECT - 24 - D23 to D20 D19 0011 0 See "Coefficient ROM Preset Values Table". CXD3017Q Command Preset Table ($348X to 34FX) Address 3 D14 0 PFOK, RFAC Booster Surf Brake Booster Servo DAC output DFCT 0 1 1 1 Address 3 D15 D14 D13 D12 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 Data 1 Data 2 Data 3 D0 -- -- 0 FCS Bias Limit FCS Bias Data Traverse Center Data --: Don't care 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 D6 D5 D4 Data 1 Data 3 Data 2 Address 1 Address 2 Register Command D23 to D20 D19 to D16 D15 1 1 1 1 1 3 SELECT 0011 0100 - 25 - CXD3017Q Command Preset Table ($35X to 3FX) Address 2 Data 1 D12 0 0 0 Data 4 D4 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 1 D3 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE AUTO GAIN DTZC/TRACK JUMP VOLTAGE AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) SERIAL DATA READ MODE/SELECT FOCUS BIAS Operation for MIRR/ DFCT/FOK 1 TZC/COUT BOTTOM/MIRR 0 0 SLED FILTER Filter Others --: Don't care Data 3 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 D7 D6 D5 0 0 0 Data 2 D12 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 D11 D10 D9 1 0 0 0 0 0 0 System GAIN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 2 Data 3 D17 D15 1 Data 1 D17 D15 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 D14 D13 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 1 1 D16 0 0 D14 D13 1 1 D16 Address 1 D18 1 Register Command D23 to D20 D19 0011 1 Address D18 1 1 1 0 0 0 0 1 1 1 1 D23 to D20 D19 0 0 0 1 3 SELECT 1 - 26 - 0011 1 1 1 1 1 1 CXD3017Q Reset Initialization Data 1 Data 4 D0 -- -- -- -- -- -- -- -- -- -- -- D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 -- Data 5 D0 D3 D3 -- -- -- D2 D1 0 0 -- -- -- -- 0 0 D2 D1 D0 D3 D2 D1 D0 0 Data 2 Data 3 Data 6 D0 -- Address Register Command D3 D2 D1 4 Auto sequence 0 1 0 5 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 1 Blind (A, E), Overflow (C) Brake (B), 0 1 0 -- -- -- -- 6 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 Kick (D) 0 1 1 -- -- -- -- -- -- 7 1 0 0 0 0 0 0 0 -- 0 0 0 1 0 0 0 0 0 Auto sequence (N) track jump count setting 0 1 1 -- -- -- -- -- -- -- 8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 MODE specification 1 0 0 0 0 0 0 0 0 0 0 9 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function specification 1 0 0 0 0 0 0 0 0 -- -- -- -- - 27 - 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 -- 1 0 0 0 1 0 0 0 0 1 0 0 0 -- 0 0 -- -- -- -- -- 1 1 0 -- -- -- -- 1 0 1 1 1 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A Audio CTRL 1 0 1 0 0 0 0 0 0 0 0 0 0 0 A Sleep setting 1 0 1 -- -- -- -- -- -- -- -- -- -- -- B Serial bus CTRL 1 0 1 -- -- -- -- -- -- -- -- -- -- -- C Spindle servo coefficient setting 1 1 0 -- -- -- -- -- -- -- -- -- -- -- D CLV CTRL 1 1 0 -- -- -- -- -- -- -- -- -- -- -- E CLV mode 1 1 1 0 0 0 -- -- -- -- -- -- -- -- CXD3017Q CXD3017Q Fix indicates that normal preset values should be used. - 28 - CXD3017Q - 29 - CXD3017Q 1-4. Description of SENS Signals and Commands SENS output Microcomputer serial register (latching not required) $0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X, 7X, 8X, 9X $AX $BX $CX $DX $EX $FX SENS output FZC AS (Anti Shock) TZC SSTP AGOK XAVEBSY TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. FBIAS count STOP SSTP XBUSY FOK 0 GFS 0 COUT frequency division 0 OV64 0 Output data length -- -- -- -- -- -- 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit -- -- -- -- -- -- -- -- -- -- -- Notes) * The SENS output can be read from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0. $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. * The signals output by $0X to $3X in the table above cannot be read during the auto sequence operation. Description of SENS Signals SENS output XBUSY FOK GFS COUT Low while the auto sequencer is in operation, high when the operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks with frequeny division ratio set by $B. High when $B is latched, and toggles each time COUT is counted just for the frequency diviison ratio set by $B. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. - 30 - OV64 CXD3017Q The meaning of the data for each address is explained below. $4X commands Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE AS3 0 0 1 1 1 1 AS2 0 1 0 0 1 1 AS1 0 1 0 1 0 1 AS0 0 1 RXF RXF RXF RXF RXF = 0 FORWARD RXF = 1 REVERSE * When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the Track jump/move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is interrupted. $5X commands Auto sequence timer setting Setting timers: A, E, C, B Command Blind (A, E), Over flow (C) Brake (B) D3 0.18ms 0.36ms D2 0.09ms 0.18ms D1 0.05ms 0.09ms D0 0.02ms 0.05ms Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset) A = E = C = 0.11ms B = 0.23ms $6X commands Auto sequence timer setting Setting timer: D Command KICK (D) D3 11.6ms D2 5.8ms D1 2.9ms D0 1.45ms Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset) D = 10.15ms $7X commands Auto sequence track jump/move count setting (N) Data 1 Command Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 29 28 27 26 25 24 23 22 21 20 Auto sequence track jump 15 14 13 12 11 10 2 2 2 2 2 2 count setting This command is used to set N when a 2N-track jump and an N-track move are executed for auto sequence. * The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. * The number of tracks jumped is counted according to the COUT signals. - 31 - CXD3017Q $8X commands Data 1 Command D3 D2 D1 D0 D3 Data 2 D2 0 D1 SOCT D0 0 D3 KSL3 Data 3 D2 KSL2 D1 1 D0 0 DOUT DOUT VCO MODE CDROM WSEL Mute ON/OFF SEL1 specification See the $BX commands. Data 4 D3 0 D2 VCO1 CS0 D1 0 D0 0 D3 0 Data 5 D2 0 D1 0 D0 0 D3 Data 6 D2 D1 D0 TXON TXOUT OUTL1 OUTL0 Command bit CDROM = 1 CDROM = 0 C2PO timing See Timing Chart 1-1. See Timing Chart 1-1. Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted. Command bit DOUT ON/OFF = 1 DOUT ON/OFF = 0 Processing Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin. Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock1 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. 1 In normal-speed playback, channel clock = 4.3218MHz. - 32 - CXD3017Q Command bit VCOSEL1 0 0 0 0 1 1 1 1 KSL3 0 0 1 1 0 0 1 1 KSL2 0 1 0 1 0 1 0 1 Processing Multiplier PLL VCO1 is set to 1x speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to 1x speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to 1x speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to 1x speed, and the output is 1/8 frequency-divided. Multiplier PLL VCO1 is set to about 2x speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to about 2x speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to about 2x speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to about 2x speed, and the output is 1/8 frequency-divided. Command bit VCO1CS0 = 0 VCO1CS0 = 1 Processing Multiplier PLL VCO1 low speed is selected. Multiplier PLL VCO1 high speed is selected. The CXD3017Q has two VCO1s, and this command selects one of these VCO1s. Block Diagram of VCO Internal Path VCO1SEL1 1/1 Low-speed VCO1 Selector Selector 1/2 To DSP interior 1/4 High-speed VCO1 VCO1CS0 1/8 KSL3, 2 VCO1 Internal Path Command bit TXON = 0 TXON = 1 Processing When CD TEXT data in not demodulated, set TXON to 0. When CD TEXT data in demodulated, set TXON to 1. See "$3-13. CD TEXT Data Demodulation" - 33 - CXD3017Q Command bit TXOUT = 0 TXOUT = 1 Processing Various signals except for CD TEXT is output from the SQSO pin. CD TEXT data is output from the SQSO pin. See "3-13. CD TEXT Data Demodulation" Command bit OUTL1 = 0 OUTL1 = 1 WFCK and XPCK are output. WFCK and XPCK outputs are low. Processing Command bit OUTL0 = 0 OUTL0 = 1 Processing PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are low. - 34 - Timing Chart 1-1 LRCK CDROM = 0 Rch 16-bit C2 Pointer Lch 16-bit C2 Pointer If C2 Pointer = 1, data is NG C2PO - 35 - C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer CDROM = 1 C2 Pointer for lower 8bits C2PO C2 Pointer for upper 8bits Lch C2 Pointer CXD3017Q CXD3017Q $9X commands (OPSL1= 0) Data 1 Command Function specification D3 0 D2 DSPB ON/OFF D1 0 Data 2 D0 and subsequent data are for DF/DAC function settings. Data 2 D0 D3 to D1 D0 0 000 0 D3 0 Data 3 D2 MCSL D1 0 D0 0 D3 Data 4 D2 D1 -- D0 -- ZDPL ZMUT OPSL1 D3 -- Data 5 D2 -- D1 -- D0 -- $9X commands (OPSL1= 1) Command Function specification Data 1 D3 0 D2 DSPB ON/OFF D1 0 Data 2 D0 and subsequent data are for DF/DAC function settings. Data 2 D0 D3 to D1 D0 0 000 0 D3 1 Data 3 D2 MCSL D1 0 D0 0 D3 Data 4 D2 D1 0 D0 0 ZDPL ZMUT OPSL1 D3 0 Data 5 D2 DCOF D1 0 D0 DAC PWDN Command bit DSPB = 1 DSPB = 0 Processing Double-speed playback (CD-DSP block) Normal-speed playback (CD-DSP block) Command bit OPSL1 = 1 OPSL1 = 0 DCOF can be set. DCOF cannot be set. Processing Command bit MCSL = 1 MCSL = 0 Processing DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz) Command bit ZDPL = 1 ZDPL = 0 Processing LMUT and RMUT pins are high when muted. LMUT and RMUT pins are low when muted. See "Mute flag output" for the mute flag output conditions. - 36 - CXD3017Q Command bit ZMUT = 1 ZMUT = 0 Zero detection mute is on. Zero detection mute is off. Processing Command bit DCOF = 1 DCOF = 0 DC offset is off. DC offset is on. Processing DCOF can be set when OPSL1 = 1. Set DC offset to off when zero detection mute is on. Command bit DACPWDN = 0 DACPWDN = 1 Normal operation. DAC block clock is stopped. This makes it possible to reduce power consumption. Data 2 and subsequent data are for DF/DAC function settings. Data 2 D0 ATT D3 0 D2 0 D1 0 D0 Data 3 D3 D2 Processing $AX commands (OPSL2 = 0) Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute EMPH SMUT AD10 OPSL2 Data 3 D1 AD9 D0 AD8 D3 AD7 Data 4 D2 AD6 D1 AD5 D0 AD4 D3 AD3 Data 5 D2 AD2 D1 AD1 D0 AD0 D3 -- Data 6 D2 -- D1 -- D0 -- $AX commands (OPSL2 = 1) Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 0 Data 2 and subsequent data are for DF/DAC function settings. Data 2 D2 0 D1 1 D0 Data 3 D3 D2 EMPH SMUT AD10 OPSL2 Data 3 D1 AD9 D0 AD8 D3 AD7 Data 4 D2 AD6 D1 AD5 D0 AD4 D3 AD3 Data 5 D2 AD2 D1 AD1 D0 D3 Data 6 D2 D1 D0 AD0 FMUT LRWO BSBST BBSL - 37 - CXD3017Q Command bit Mute = 1 Mute = 0 Processing CD-DSP block mute is on. 0 data is output from the CD-DSP block. CD-DSP block mute is off. Command bit ATT = 1 ATT = 0 Processing CD-DSP block output is attenuated (-12dB). CD-DSP block output attenuation is off. Command bit OPSL2 = 1 OPSL2 = 0 Meaning FMUT, LRWO, BSBST and BBSL can be set. FMUT, LRWO, BSBST and BBSL cannot be set. Command bit EMPH = 1 EMPH = 0 De-emphasis is on. De-emphasis is off. Processing If either the EMPHI pin or EMPH is high, de-emphasis is on. Command bit SMUT = 1 SMUT = 0 Soft mute is on. Soft mute is off. Processing If either the SMUT pin or SMUT is high, soft mute is on. Command bit AD10 to 0 Attenuation data. Meaning The attenuation data consists of 11 bits, and is set as follows. Attenuation data 400h 3FEh 3FDh : 001h 000h Audio output 0dB -0.0085dB -0.0170dB -60.206dB - Audio output = 20log The attenuation data (AD10 to AD0) consists of 11bits, and can be set in 1024 different ways in the range of 000h to 400h. The audio output from 001h to 400h is obtained using the following equation. Attenuation data [dB] 1024 - 38 - CXD3017Q Command bit FMUT = 1 FMUT = 0 Forced mute is on. Forced mute is off. Meaning FMUT can be set when OPSL2 = 1. Command bit LRWO = 1 LRWO = 0 Forced synchronization mode Note) Normal operation. Meaning LRWO can be set when OPSL2 = 1. Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1. Command bit BSBST = 1 BSBST = 0 Bass boost is on. Bass boost is off. Processing BSBST can be set when OPSL2 = 1. Command bit BBSL = 1 BBSL = 0 Bass boost is Max. Bass boost is Mid. Processing BBSL can be set when OPSL2 = 1. - 39 - CXD3017Q $AD commands (preset: $AD00) Data 1 Command AD (Sleep setting) ADCPS: D3 1 D2 1 D1 0 D0 1 D3 ADCPS Data 2 D2 D1 D0 D3 0 Data 3 D2 LPF SLEEP D1 0 D0 0 D3 Data 4 D2 D1 D0 DSP DSSP ASYM SLEEP SLEEP SLEEP This bit sets the operating mode of the DSSP block A/D converter. When 0, the operating mode of the DSSP block A/D converter is set to normal. (default) When 1, the operating mode of the DSSP block A/D converter is set to power saving. DSP SLEEP: This bit sets the operating mode of the DSP block. When 0, the DSP block operates normally. (default) When 1, the DSP block clock is stopped. This makes it possible to reduce power consumption. DSSP SLEEP: This bit sets the operating mode of the DSSP block. When 0, the DSSP block operates normally. (default) When 1, the DSSP block clock is stopped. In addition, the A/D converter and operational amplifier in the DSSP block are set to standby mode. This makes it possible to reduce power consumption. ASYM SLEEP: This bit sets the operating mode of the asymmetry correction circuit and VCO1. When 0, the asymmetry correction circuit and VCO1 operate normally. (default) When 1, the operational amplifier in the asymmetry correction circuit is set to standby mode. In addition, the multiplier PLL VCO1 oscillation is stopped. This makes it possible to reduce power consumption. LPF SLEEP: This bit sets the operating mode of the analog low-pass filter block. When 0, the analog low-pass filter block operates normally. (default) When 1, the analog low-pass filter block is set to standby mode. This makes it possible to reduce power consumption. The DAC block clock can be stopped by setting $9 command DACPWDN (when OPSL1 = 1). - 40 - $BX commands Data 2 D0 D2 D0 0 TRM1 TRM0 MTSL1 MTSL0 D3 D1 Command Data 1 D3 D2 D1 Serial bus CTRL SL1 SL0 CPUSR SOCT SL1 SL0 mode 0 0 0 SubQ 0 0 1 Peak meter 0 1 0 SENS The SQSO pin output can be switched to the various signals by setting the SOCT command of $8X and the SL1 and SL0 commands of $BX. Set SQCK to high at the falling edge of XLAT. Except for Sub Q and peak meter, the signals are loaded to the register when they are set at the falling edge of XLAT. Sub Q is loaded to the register with each SCOR, and Peak meter is loaded when a peak is detected. 0 1 1 D 1 0 0 SubQ 1 0 1 A 1 1 0 B - 41 - PER4 PER5 PER6 PER7 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS LOCK -- -- -- -- -- -- ALOCK C1F1 C1F2 0 C2F1 C2F2 0 FOK PER3 PER4 PER5 PER6 PER7 0 C1F1 C1F2 0 C2F1 C2F2 0 FOK 0 WFCK SCOR GFS GTOP EMPH FOK LOCK RFCK XRAOF C1F1 C1F2 C2F1 C2F2 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 1 1 1 C --: don't care XLAT SQCK mode A PER0 PER1 PER2 PER3 EMPH ALOCK -- -- -- -- -- -- -- -- mode B -- -- GFS LOCK EMPH mode C PER0 PER1 PER2 GFS LOCK EMPH mode D SPOA SPOB 0 CXD3017Q Peak meter L0 L1 CXD3017Q Signal PER0 to 7 FOK GFS LOCK EMPH ALOCK SPOA, B WFCK SCOR GTOP RFCK XRAOF L0 to L7, R0 to R7 Description RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. SPOA and B pin inputs. Write frame clock output. High when either subcode sync S0 or S1 is detected. High when the sync protection window is open. Read frame clock output. Low when the built-in 16K RAM exceeds the 4 frame jitter margin. Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak data. L0 and R0 are LSB. C1F1 0 1 1 C1F2 0 0 1 C1 correction status No Error Single Error Correction Irretrievable Error C2F1 0 1 1 C2F2 0 0 1 C2 correction status No Error Single Error Correction Irretrievable Error Command bit CPUSR = 1 CPUSR = 0 XLON pin is high. XLON pin is low. Processing - 42 - CXD3017Q Peak meter XLAT SQCK SQSO (Peak meter) L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively, results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16 clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270s to 400s. The time during which SQCK input is high should be 270s or less. Also, peak detection is restarted 270s to 400s after SQCK input. The peak register is reset with each readout (16 clocks input to SQCK). The maximum value in peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak register. Peak detection can also be performed for previous value hold and average value interpolation data. Traverse monitor count value setting These bits are set when monitoring the traverse condition of the SENS output according to the COUT frequency division. Command bit TRM1 0 0 1 1 TRM0 0 1 0 1 1/64 frequency division 1/128 frequency division 1/256 frequency division 1/512 frequency division Processing Monitor output switching The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B. Output data Symbol Command bit MTSL1 0 0 1 MTSL0 0 1 0 XUGF MNT1 RFCK XPCK MNT0 XPCK GFS MNT3 XROF C2PO C2PO GTOP XUGF XPCK GFS C2PO It is necessary for the SRO1 command of $3F to be set to 0. - 43 - CXD3017Q $CX commands Command Servo coefficient setting CLV CTRL ($DX) D3 Gain MDP1 D2 Gain MDP0 D1 Gain MDS1 D0 Gain MDS0 Gain CLVS * CLV mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB * CLVP mode gain setting: GMDP: GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB $DX commands Command CLV CTRL Data 1 D3 0 D2 TB D1 TP D0 Gain CLVS D3 1 Data 2 D2 1 D1 1 D0 0 D3 0 Data 3 D2 0 D1 0 D0 0 See the $CX commands. Command bit TB = 0 TB = 1 TP = 0 TP = 1 Description Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. - 44 - CXD3017Q $EX commands Data 1 Command CLV mode D3 CM3 D2 CM2 D1 CM1 D0 CM0 D3 0 Data 2 D2 0 D1 0 D0 0 D3 0 Data 3 D2 0 D1 0 D0 0 Data 4 D3 0 D2 0 D1 0 D0 0 Command bit CM3 0 1 1 CM2 0 0 0 CM1 0 0 1 CM0 0 0 0 Mode STOP KICK BRAKE Spindle stop mode.1 Description Spindle forward rotation mode.1 Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. 1 1 0 1 1 1 1 1 1 0 1 0 CLVS CLVP CLVA 1 See Timing Charts 1-2 and 1-3. Timing Chart 1-2 KICK H Z KICK Z MDP L BRAKE MDP Z BRAKE STOP MDP STOP Timing Chart 1-3 n * 236 (ns) n = 0 to 31 Acceleration MDP Z Deceleration 132kHz 7.6s - 45 - CXD3017Q 2. Subcode Interface In the CXD3017Q, only SubQ can be readout. The subcodes P and R to W cannot be readout. Sub Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. 2-1. 80-bit Sub Q Readout Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high 400s (monostable multivibrator time constant) or more after subcode readout, the CPU determines that the new data (which passed the CRC check) has been loaded. * The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump, etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been loaded. * When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. * While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. (See Timing Chart 2-2.) * The high and low intervals for SQCK should be between 750ns and 120s. - 46 - Block Diagram 2-1 (AFRAM) (ASEC) (AMIN) ADDRS CTRL SUBQ 80bit S/P Register SIN ABCDEFGH 8 8 8 8 8 8 Order Inversion 8 8 8 HGFEDCBA 80bit P/S Register SO LD LD LD LD LD SUBQ LD CRCC Mono/Multi SHIFT LD LD SI - 47 - SHIFT SQCK CRCF Mix SQSO CXD3017Q Timing Chart 2-2 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK Order Inversion Determined by mode L 80 Clock CRCF2 SCOR SQSO CRCF1 SQCK Registere load forbidder - 48 - 750ns to 120s 270 to 400s when SQCK = high. ADR0 ADR1 ADR2 ADR3 300ns max Mono/multi (Internal) SQCK SQSO CRCF CTL0 CTL1 CTL2 CTL3 CXD3017Q CXD3017Q 3. Description of Other Functions 3-1. Channel Clock Regeneration by the Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 3-1. The CXD3017Q has a built-in three-stage PLL. * The first-stage PLL regenerates the high-frequency clock needed by the second-stage digital PLL. * The second-stage PLL is a digital PLL that regenerates the actual channel clock. Block Diagram 3-1 X'tal OSC 1/M Phase comparator PCO XTSL 1/N FILI FILO 1/K (KSL3, 2) CLTV VCO1 Digital PLL RFPLL CXD3017Q VCOSEL1 - 49 - CXD3017Q 3-2. Frame Sync Protection * In normal-speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD3017Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. 3-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. * The CXD3017Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. * The correction status can be monitored externally. See Table 3-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 1 1 1 MNT1 0 0 1 0 0 1 MNT0 0 1 1 0 1 0 Description No C1 errors One C1 error corrected C1 correction impossible No C2 errors One C2 error corrected C2 correction impossible Table 3-2 - 50 - CXD3017Q Timing Chart 3-3 Normal-speed PB t = Dependent on error condition MNT3 C1 correction C2 correction MNT1 MNT0 Strobe Strobe 3-4. DA Interface * The CXD3017Q's DA interface is as follows: Interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. - 51 - Timing Chart 3-4 48-bit slot Normal-Speed Playback LRCK (44.1k) 5 6 7 8 9 10 11 12 24 1 2 3 4 BCK (2.12M) PCMD L14 L13 L12 L11 L10 L9 L8 L7 L6 R0 Lch MSB (15) L5 L4 L3 L2 L1 L0 RMSB 48-bit slot Double-Speed Playback - 52 - 24 Rch MSB L0 LRCK (88.2k) 1 2 BCK (4.23M) PCMD Lch MSB (15) R0 CXD3017Q CXD3017Q 3-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3017Q supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3) of the channel status. When Mute = 1 in $AX commands, the channel status is pre-value hold. Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q 32 48 0 176 Bits 0 to 3 Sub Q control bits that matched twice with CRCOK Table 3-5 3-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed automatically. The commands which enable transfer to the CXD3017Q during the execution of auto sequence are $4X to $EX. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. - 53 - CXD3017Q (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. Auto focus Focus search up FOK = H YES NO (Check whether FZC is continuously high for the period of time E set with register 5.) FZC = H YES NO FZC = L YES Focus servo ON NO END Fig. 3-6-(a). Auto Focus Flow Chart - 54 - CXD3017Q $47latch XLAT FOK (FZC) BUSY Command for DSSP $03 Blind E $08 Fig. 3-6-(b). Auto Focus Timing Chart (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 3-7. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 3-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 3-9. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. * N-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance with Fig. 3-10. N can be set to 216 tracks. COUT is used for counting the number of jumps. The N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. - 55 - CXD3017Q Track Track FWD kick sled servo OFF WAIT (Blind A) (REV kick for REV jump) COUT = NO YES Track REV kick WAIT (Brake B) Track, sled servo ON (FWD kick for REV jump) END Fig. 3-7-(a). 1-Track Jump Flow Chart $48 (REV = $49) latch XLAT COUT BUSY Blind A Command for DSSP $28 ($2C) $2C ($28) Brake B $25 Fig. 3-7-(b). 1-Track Jump Timing Chart - 56 - CXD3017Q 10 Track Track, sled FWD kick WAIT (Blind A) COUT = 5 ? YES Track, REV kick NO (Counts COUT x 5) C = Overflow ? YES Track, sled servo ON NO (Check whether the COUT cycle is longer than overflow C.) END Fig. 3-8-(a). 10-Track Jump Flow Chart $4A (REV = $4B) latch XLAT COUT BUSY Blind A Command for DSSP COUT 5 counts Overflow C $2A ($2F) $2E ($2B) $25 Fig. 3-8-(b). 10-Track Jump Timing Chart - 57 - CXD3017Q 2N Track Track, sled FWD kick WAIT (Blind A) COUT = N NO YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Fig. 3-9-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) latch XLAT COUT BUSY Blind A Command for DSSP $2A ($2F) COUT N counts $2E ($2B) Overflow C $26 ($27) Kick D $25 Fig. 3-9-(b). 2N-Track Jump Timing Chart - 58 - CXD3017Q N Track move Track servo OFF Sled FWD kick WAIT (Blind A) COUT = N NO YES Track, sled servo OFF END END Fig. 3-10-(a). N-Track Move Flow Chart $4E (REV = $4F) latch XLAT COUT BUSY Blind A Command for DSSP $22 ($23) COUT N counts $20 Fig. 3-10-(b). N-Track Move Timing Chart - 59 - CXD3017Q 3-7. Digital CLV Fig. 3-11 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Oversampling Filter-1 Gain MDS 1/2 MUX Gain MDP CLV P/S Oversampling Filter-2 Noise Shape KICK, BRAKE, STOP Modulation MDP CLVS U/D: Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo Fig. 3-11. Block Diagram - 60 - CXD3017Q 3-8. CD-DSP Block Playback Speed In the CXD3017Q, the following playback modes can be selected through different combinations of the crystal, XTSL pin and the DSPB command of $9X. CD-DSP block playback speed Crystal 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 0 1 1 0 0 1 DSPB 1 0 1 0 1 1 CD-DSP block playback speed 4x1 1x 2x 1x 2x 1x2 Fs = 44.1kHz. 1 In 4x speed playback, the timer value for the auto sequence is halved. 2 Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption to be reduced. 3-9. DAC Block Playback Speed The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC and CD-DSP blocks to be set independently. 1-bit DAC block playback speed Crystal 768Fs 768Fs 384Fs Fs = 44.1kHz. MCSL 1 0 0 DAC block playback speed 1x 2x 1x - 61 - CXD3017Q 3-10. Description of DAC Block Functions Zero data detection When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently for the left and right channels. Mute flag output The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected with the ZDPL command of $9X. * When zero data is detected * When a high signal is input to the SYSM pin * When the SMUT command of $AX is set Attenuation operation Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1 continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches Y3 from the value (B or C in the figure) at that point. 0dB 3FF (H) A Y1 B Y3 C Y2 - 000 (H) 23.2 [ms] - 62 - CXD3017Q DAC block mute operation Soft mute Soft mute results and the input data is attenuated to zero when any one of the following conditions is met. * When attenuation data of "000" (high) is set * When the SMUT command of $AX is set to 1 * When a high signal is input to the SYSM input pin Soft mute off 0dB Soft mute on Soft mute off - dB 23.2 [ms] 23.2 [ms] Forced mute Forced mute results when the FMUT command of $AX is set to 1. Forced mute fixes the PWM output that is input to the LPF block to low. When setting FMUT, set OPSL2 to 1. (See the $AX commands.) Zero detection mute When the ZMUT command of $9X is set to 1 and the zero data is detected for the left or right channel, the analog mute is applied to the each channel. (See "Zero data detection".) When the ZMUT command of $9X is set to 1, the analog mute is applied even if the mute flag output condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1. - 63 - CXD3017Q LRCK Synchronization Synchronization is performed at the first falling edge of the LRCK input during reset. After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases. * When the XTSL pin switches between high and low * When the DSPB command of $9X setting changes * When the MCSL command of $9X setting changes LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in this case as well. For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set LRWO to 0. When setting LRWO, set OPSL2 to 1. (See the $AX commands.) Digital Bass Boost Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: Mid. and Max. BSBST and BBSL of address A are used for the setting. See Graph 3-12 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 Normal DBB MID DBB MAX [dB] -2.00 -4.00 -6.00 -8.00 -10.00 -12.00 -14.00 10 30 100 300 1k 3k 10k 30k Digital Bass Boost Frequency Response [Hz] Graph 3-12 - 64 - CXD3017Q 3-11. LPF Block The CXD3017Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (VC) is (AVDD - AVSS) x 0.45. The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc 40kHz. LPF Block Application Circuit AOUT1 (2) 27k C2 330p AIN1 (2) Vc C1 68p 27k 27k 100 Analog out LOUT1 (2) Fig. 3-13. LPF External Circuit - 65 - CXD3017Q 3-12. Asymmetry Compensation Fig. 3-14 shows the block diagram and circuit example. CXD3017Q ASYO R1 RFAC R1 R2 R1 ASYI R1 BIAS R1 = 2 R2 5 Fig. 3-14. Asymmetry Compensation Application Circuit - 66 - CXD3017Q 3-13. CD TEXT Data Demodulation * In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1. * The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK. * The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except for CRC data. * When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Data which can be stored in the LSI is 1 packet (4 packs). CD TEXT Decoder Subcode Decoder SQCK SQSO TXOUT Fig. 3-15. Block Diagram of CD TEXT Demodulation Circuit - 67 - SCOR Subcode Q Data CRC 80 clocks 520 clocks 0 Pack1 Pack3 Pack2 Pack4 4 bits 16 Bytes 4 bits 16 Bytes 16 Bytes 16 Bytes CRCF SQSO CRCF SQCK TXOUT (command) - 68 - ID1 (Pack1) LSB 1 CRC Data MSB LSB R2 W1 V1 U1 T1 S1 R1 U3 T3 ID2 (Pack1) MSB S3 R3 W2 V2 U2 LSB ID3 (Pack1) SQSO CRC CRC CRC CRC 4 3 2 0 0 S2 0 0 T2 W4 V4 U4 T4 S4 SQCK TXOUT (command) CXD3017Q Fig. 3-16. CD TEXT DATA Timing Chart CXD3017Q 4. Description of Servo Signal Processing System Functions and Commands 4-1. General Description of Servo Signal Processing System (VDD: Supply voltage) Focus servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 1/4VDD to 3/4VDD 7-bit PWM Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control Tracking servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 1/4VDD to 3/4VDD 7-bit PWM Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: Input range: Output format: Other: 345Hz (when MCK = 128Fs) 1/4VDD to 3/4VDD 7-bit PWM Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Other: RF zero level automatic measurement - 69 - CXD3017Q 4-2. Digital Servo Block Master Clock (MCK) The clock with 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is a $3E command. (Default is 0 for each command) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode 1 2 3 4 5 6 7 XTAI 384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs FSTO 256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs XTSL 0 1 XT4D 0 1 0 XT2D 1 0 1 0 0 Table 4-1 XT1D 1 0 0 1 0 0 0 Frequency division ratio 1 1/2 1/2 1 1/2 1/4 1/4 MCK 256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs Fs = 44.1kHz, : don't care - 70 - CXD3017Q 4-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 4-3.) The CXD3017Q can measure the averages of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3017Q, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TLM) of $38. Measurement is on when the respective command is set to 1. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 4-2.) Monitoring requires that the upper 8 bits of the command register are 38 (h). XLAT 2.9 to 5.8ms SENS (= XAVEBSY) Max. 1s AVRG measurement completed Timing Chart 4-2 CXD3017Q 4-4. E:F Balance Adjustment Function (See Fig. 4-3.) When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS search, the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 4-3.) 4-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 4-3.) When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the $8 command SOCT to 1. (See "DSP Block Timing Chart".) - 72 - CXD3017Q RFDC from A/D RF AVRG register - RFLC to RF In register SE from A/D - TLC1 * TLD1 TLC2 * TLD2 - to SLD In register TE from A/D - - to TRK In register TE AVRG register TLC1 TRVSC register TLC2 FE from A/D FE AVRG register - FLC1 FBIAS register + FBON to FCS In register FLC0 - to FZC register Fig. 4-3a RFDC from A/D RF AVRG register - RFLC to RF In register SE from A/D - TLC0 * TLD0 TLC2 * TLD2 - to SLD In register TE from A/D - TLC0 VC AVRG register TRVSC register TLC2 - to TRK In register VCLC FE from A/D FE AVRG register - + FLC0 FBIAS register FBON to FCS In register - to FZC register Fig. 4-3b - 73 - CXD3017Q 4-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (h), the completion of AGCNTL operation can be confirmed by monitoring the SENS pin. (See Timing Chart 4-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 sets FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4s SENS (= AGOK) AGCNTL completion Timing Chart 4-4 Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (h), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (h) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (h) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0 dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. - 74 - CXD3017Q AGCNTL default operation has two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3017Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 4-5. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Convergence value AGHT AGCNTL Start SENS AGJ AGCNTL completion Fig. 4-5 Note) Fig. 4-5 shows the case where the AGCCNTL coefficient converges from the initial value to a smaller value. - 75 - CXD3017Q 4-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 4-6.) Register name Command D23 to D20 D19 to D16 10 11 0 FOCUS CONTROL 0 0 00 00 01 010 011 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP : don't care Table 4-6 FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 4-7 shows the signals for sending commands $00 $02 $03 and performing only FCS search operation. Fig. 4-8 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 $08 0 FCSDRV FCSDRV RF FOK FZC comparator level FE 0 RF FOK FE 0 FZC FZC Fig. 4-7 Fig. 4-8 - 76 - CXD3017Q 4-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 4-9.) When the upper 4 bits of the serial data are 2 (h), TZC is output to the SENS pin. Register name Command D23 to D20 D19 to D16 00 01 10 2 TRACKING MODE 0010 11 00 01 10 11 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE : don't care Table 4-9 TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3017Q has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 4-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1x, 2x, 3x, or 4x set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 4-10.) SLD MOV must be performed continuously for 50s or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name Command D23 to D20 D19 to D16 0000 3 SELECT 0011 0001 0010 0011 SLED KICK LEVEL (basic value x 1) SLED KICK LEVEL (basic value x 2) SLED KICK LEVEL (basic value x 3) SLED KICK LEVEL (basic value x 4) Table 4-10 - 77 - CXD3017Q 4-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 4-11.) The bottom hold speed and mirror sensitivity can be selected from four values using D7 and D6, and D5 and D4, respectively, of $3C. RF Peak Hold Bottom Hold Peak Hold - Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 4-11 DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 4-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold - Bottom Hold SDF (Defect comparator level) H DFCT L Fig. 4-12 - 78 - CXD3017Q 4-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, this operation is achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 4-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Hold filter Error signal Input register DFCT Hold register EN Servo filter Fig. 4-13 4-11. Anti-Shock Circuit When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 4-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 4-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (h), vibration detection can be monitored from the SENS pin. It can also be monitored from the ATSK pin by setting $3F command ASOT to 1. ATSK TE Anti shock filter Comparator SENS TRK Gain Up filter TRK Gain Normal filter TRK PWM Gen. Fig. 4-14 - 79 - CXD3017Q 4-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 4-15 and 4-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Table 4-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B) Inner track Outer track FWD REV Servo ON JMP JMP TRK DRV TRK DRV Outer track Inner track REV FWD Servo ON JMP JMP RF Trace MIRR TE 0 RF Trace MIRR TE 0 TZC Edge TRKCNCL TRK DRV (SFBK OFF) TRK DRV (SFBK ON) SENS TZC out 0 TZC Edge TRKCNCL TRK DRV (SFBK OFF) TRK DRV (SFBK ON) SENS TZC out 0 0 0 Fig. 4-15 Register name Fig. 4-16 Command D23 to D20 D19 to D16 10 0 1 0 0 1 1 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 : don't care 1 TRACKING CONTROL 0001 Table 4-17 - 80 - CXD3017Q 4-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application. * HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.) * STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation. This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) * DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C. When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC When DTZC is selected, the delay can be selected from two values with D14 of $36. 4-14. Serial Readout Circuit The following measurement and adjustment results specified beforehand by serial command $39 can be read out from the SENS pin by inputting the readout clock to the SCLK pin. (See Fig. 4-18, Table 4-19 and "Description of SENS Signals".) Specified commands $390C: VC AVRG measurement result $3908: FE AVRG measurement result $3904: TE AVRG measurement result $391F: RF AVRG measurement result XLAT tDLS $3953: FCS AGCNTL coefficient result $3963: TRK AGCNTL coefficient result $391C: TRVSC adjustment result $391D: FBIAS register value tSPW SCLK 1/fSCLK Serial Readout Data (SENS pin) ... MSB ... LSB Fig. 4-18 Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 31.3 15 Table 4-19 During readout, the upper 8 bits of the command register must be 39 (h). - 81 - Unit MHz ns s tSPW tDLS CXD3017Q 4-15. Writing to Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40s (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as the data. Coefficient rewriting is completed 11.3s (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients continuously, be sure to wait 11.3s (when MCK = 128Fs) before sending the next rewrite command. 4-16. PWM Output FCS, TRK and SLD PWM format outputs are described below. In particular, FCS and TRK use a double oversampling noise shaper. Timing Chart 4-20 and Fig. 4-21 show examples of output waveforms and drive circuits. MCK (5.6448MHz) SLD 64tMCK SFDR SRDR AtMCK AtMCK 64tMCK 64tMCK Output value +A Output value -A Output value 0 FCS/TRK 32tMCK FFDR/ TFDR FRDR/ TRDR A tMCK 2 32tMCK A tMCK 2 A tMCK 2 A tMCK 2 32tMCK 32tMCK 32tMCK 32tMCK tMCK = 1 180ns 5.6448MHz Timing Chart 4-20 VCC R R RDR FDR R R VEE DRV Fig. 4-21. Drive Circuit - 82 - CXD3017Q 4-17. Servo Status Changes Produced by LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. 4-18. Description of Commands and Data Sets $34 D15 0 D14 KA6 D13 KA5 D12 KA4 D11 KA3 D10 KA2 D9 KA1 D8 KA0 D7 KD7 D6 KD6 D5 KD5 D4 KD4 D3 KD3 D2 KD2 D1 KD1 D0 KD0 When D15 = 0. KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data $348 (preset: $348 000) D15 1 D14 0 D13 0 D12 0 D11 0 D10 0 D9 D8 D7 0 D6 0 D5 0 D4 D3 D2 D1 0 D0 0 PFOK1 PFOK0 MRS MRT1 MRT0 These commands set the FOK signal hold time. See $3B for the FOK slice level. These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting. PFOK1 0 0 1 1 MRS: PFOK0 0 1 0 1 Processing High when the RFDC value is higher than the FOK slice level, low when lower than the FOK slice level. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 4.35ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 10.16ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 21.77ms or more. MRT1, 0: This command switches the time constant for generating the MIRR comparator level of the MIRR generation circuit. When 0, the time constant is normal. (default) When 1, the time constant is longer than normal. The time during which MIRR = high due to the effects of RFDC signal pulse noise, etc., can be suppressed by setting MRS = 1. These commands limit the time while MIRR = high. MRT2 0 0 1 1 MRT1 0 1 0 1 MIRR maximum time [ms] No time limit 1.10 2.20 4.00 : preset - 83 - CXD3017Q $34B (preset: $34B 000) D15 1 D14 0 D13 1 D12 1 D11 D10 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SFBK1 SFBK2 The low frequency can be boosted for brake operation. See 4-12 for brake operation. SFBK1: SFBK2: When 1, brake operation is performed by setting the LowBooster-1 input to 0. This is valid only when TLB1ON = 1. Preset is 0. When 1, brake operation is performed by setting the LowBooster-2 input to 0. This is valid only when TLB2ON = 1. Preset is 0. $34C (preset: $34C 000) D15 1 D14 1 D13 0 D12 0 D11 D10 D9 D8 D7 D6 0 D5 D4 D3 D2 D1 D0 THBON FHBON TLB1ON FLB1ON TLB2ON HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 These bits turn on the boost function. (See 4-20. Filter Composition.) There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off independently. THBON: FHBON: TLB1ON: FLB1ON: TLB2ON: When 1, the high frequency is boosted for the TRK filter. Preset is 0. When 1, the high frequency is boosted for the FCS filter. Preset is 0. When 1, the low frequency is boosted for the TRK filter. Preset is 0. When 1, the low frequency is boosted for the FCS filter. Preset is 0. When 1, the low frequency is boosted for the TRK filter. Preset is 0. The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted. For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump. The following commands set the boosters. (See 4-20. Filter Composition.) HBST1, HBST0: TRK and FCS HighBooster setting. HighBooster has the configuration shown in Fig. 4-22a, and can select three different combinations of coefficients BK1, BK2 and BK3. (See Table 4-23a.) An example of characteristics is shown in Fig. 4-24a. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB1S1, LB1S0: TRK and FCS LowBooster-1 setting. LowBooster-1 has the configuration shown in Fig. 4-22b, and can select three different combinations of coefficients BK4, BK5 and BK6. (See Table 4-23b.) An example of characteristics is shown in Fig. 4-24b. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB2S1, LB2S0: TRK LowBooster-2 setting. LowBooster-2 has the configuration shown in Fig. 4-22c, and can select three different combinations of coefficients BK7, BK8 and BK9. (See Table 4-23c.) An example of characteristics is shown in Fig. 4-24c. This booster is used exclusively for the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs). Note) Fs = 44.1kHz - 84 - CXD3017Q BK3 Z-1 BK1 Z-1 BK2 HighBooster setting HBST1 0 1 1 HBST0 -- 0 1 BK1 -120/128 -124/128 -126/128 BK2 96/128 112/128 120/128 BK3 2 2 2 Fig. 4-22a Table 4-23a BK6 Z-1 BK4 Z-1 BK5 LowBooster-1 setting LB1S1 0 1 1 LB1S0 -- 0 1 BK4 -255/256 -511/512 -1023/1024 BK5 1023/1024 2047/2048 4095/4096 BK6 1/4 1/4 1/4 Fig. 4-22b Table 4-23b BK9 Z-1 BK7 Z-1 BK8 LowBooster-12 setting LB2S1 0 1 1 LB2S0 -- 0 1 BK7 -255/256 -511/512 -1023/1024 BK8 1023/1024 2047/2048 4095/4096 BK9 1/4 1/4 1/4 Fig. 4-22c Table 4-23c - 85 - CXD3017Q 15 12 9 3 6 3 2 1 Gain [dB] 0 -3 -6 -9 -12 -15 1 10 100 Frequency [Hz] 1k 10k +90 +72 3 2 1 +36 Phase [degree] 0 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 4-24a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs) 1 HBST1 = 0 2 HBST1 = 1, HBST0 = 0 - 86 - 3 HBST1 = 1, HBST0 = 1 CXD3017Q 15 12 9 6 3 Gain [dB] 3 0 -3 -6 -9 -12 -15 2 1 1 10 100 Frequency [Hz] 1k 10k +90 +72 +36 Phase [degree] 3 0 2 1 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 4-24b. Servo LowBooster-1 characteristics [FCS, TRK] (MCK = 128Fs) 1 LB1S1 = 0 2 LB1S1 = 1, LB1S0 = 0 - 87 - 3 LB1S1 = 1, LB1S0 = 1 CXD3017Q 15 12 9 6 3 Gain [dB] 3 0 -3 -6 -9 -12 -15 2 1 1 10 100 Frequency [Hz] 1k 10k +90 +72 +36 Phase [degree] 3 0 2 1 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 4-24c. Servo LowBooster-2 characteristics [TRK] (MCK = 128Fs) 1 LB2S1 = 0 2 LB2S1 = 1, LB2S0 = 0 - 88 - 3 LB2S1 = 1, LB2S0 = 1 CXD3017Q $34E (preset: $34E000) D15 1 IDFSL3: D14 1 D13 1 D12 0 D11 D10 D9 D8 D7 0 D6 0 D5 D4 D3 0 D2 0 D1 0 D0 INVRFDC IDFSL3 IDFSL2 IDFSL1 IDFSL0 IDFT1 IDFT0 New DFCT detection output setting. When 0, only the DFCT signal described in 4-9 is detected and output from the DFCT pin. (default) When 1, the DFCT signal described in 4-9 and the new DFCT signal are switched and output from the DFCT pin. The switching timing is as follows. When the 4-9 DFCT signal is low, the new DFCT signal is output from the DFCT pin. When the 4-9 DFCT signal is high, this DFCT signal is output from the DFCT pin. In addition, the time at which the new DFCT signal can be output after the 4-9 DFCT signal switches to low can also be set. (See IDFT1, 0 of $34E.) IDFSL3 0 0 1 1 4-9 DFCT L H L H DFCT pin 4-9 DFCT 4-9 DFCT New DFCT 4-9 DFCT IDFSL2: IDFSL1: IDFSL0: IDFT1, 0: New DFCT detection time setting. DFCT = high is held for a certain time after new DFCT detection. This command sets that time. When 0, a long hold time. (default) When 1, a short hold time. New DFCT detection sensitivity setting. When 0, a high detection sensitivity. (default) When 1, a low detection sensitivity. New DFCT release sensitivity setting. When 0, a high release sensitivity. (default) When 1, a low release sensitivity. These commands set the time at which the new DFCT signal can be output (output prohibited time) after the 4-9 DFCT signal switches to low. IDFT1 0 0 1 1 IDFT0 0 1 0 1 New DFCT signal output prohibited time 204.08s 294.78s 408.16s 612.24s : preset INVRFDC: RFDC signal polarity inverted input setting. When 0, the RFDC signal polarity is set to non-inverted. (default) When 1, the RFDC signal polarity is set to inverted. - 89 - CXD3017Q $34F D15 1 D14 1 D13 1 D12 1 D11 1 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1. D15 1 D14 1 D13 1 D12 1 D11 0 D10 1 D9 FB9 D8 FB8 D7 FB7 D6 FB6 D5 FB5 D4 FB4 D3 FB3 D2 FB2 D1 FB1 D0 -- When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; two's complement data, FB9 = MSB. For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 x VDD/4 and FB9 to FB1 = 100000000 to -256/256 x VDD/4 respectively. (VDD: supply voltage) D15 1 D14 1 D13 1 D12 1 D11 0 D10 0 D9 TV9 D8 TV8 D7 TV7 D6 TV6 D5 TV5 D4 TV4 D3 TV3 D2 TV2 D1 TV1 D0 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; two's complement data, TV9 = MSB. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 x VDD/4 and TV9 to TV0 = 1100000000 to -256/256 x VDD/4 respectively. (VDD: supply voltage) Notes) * When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit TV8 to TV0 during external write are read out. * When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. - 90 - CXD3017Q $35 (preset: $35 58 2D) D15 FT1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 D10 FS2 D9 FS1 D8 FS0 D7 FTZ D6 FG6 D5 FG5 D4 FG4 D3 FG3 D2 FG2 D1 FG1 D0 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (0.673 x VDDV/s) Focus drive output conversion FT1 0 0 1 1 0 0 1 1 FT0 0 1 0 1 0 1 0 1 FTZ 0 0 0 0 1 1 1 1 Focus search speed [V/s] 1.35 x VDD 0.673 x VDD 0.449 x VDD 0.336 x VDD 1.79 x VDD 1.08 x VDD 0.897 x VDD 0.769 x VDD : preset, VDD: PWM driver supply voltage FS5 to FS0: FG6 to FG0: Focus search limit voltage Default value: 011000 ((1 24/64) x VDD/2, VDD: PWM driver supply voltage) Focus drive output conversion AGF convergence gain setting value Default value: 0101101 $36 (preset: $36 0E 2E) D15 0 DTZC: TJ5 to TJ0: D14 D13 D12 TJ4 D11 TJ3 D10 TJ2 D9 TJ1 D8 D7 D6 D5 TG5 D4 TG4 D3 TG3 D2 TG2 D1 TG1 D0 TG0 DTZC TJ5 TJ0 SFJP TG6 SFJP: TG6 to TG0: DTZC delay (8.5/4.25s, when MCK = 128Fs) Default value: 0 (4.25s) Track jump voltage Default value: 001110 ((1 14/64) x VDD/2, VDD: PWM driver supply voltage) Tracking drive output conversion Surf jump mode on/off The tracking PWM output is generated by adding the tracking filter output and TJReg (TJ5 to TJ0), by setting D7 to 1 (on) AGT convergence gain setting value Default value: 0101110 - 91 - CXD3017Q $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 x VDD/2, VDD: supply voltage); FE input conversion FZSH 0 0 1 1 FZSL 0 1 0 1 Slice level 1/4 x VDD/2 1/8 x VDD/2 1/16 x VDD/2 1/32 x VDD/2 : preset SM5 to SM0: Sled move voltage Default value: 010000 ((1 16/64) x VDD/2, VDD: PWM driver supply voltage) Sled drive output conversion AGCNTL self-stop on/off Default value: 1 (on) AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF AGGT 0 (small) 1/32 x VDD/2 1 (large) 1/16 x VDD/2 0 (small) 1/16 x VDD/2 1 (large) 1/8 x VDD/2 : preset AGV1: AGV2: AGHS: AGHT: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) AGS: AGJ: AGGF: AGGT: - 92 - CXD3017Q $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC offset cancel. See 4-3. VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) Automatic gain control. See 4-6. AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off) Misoperation prevention circuit DFSW: Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. LKSW: Lock switch (on/off) Setting this switch to 1 (on) disables the sled free-running prevention circuit. DC offset cancel. See 4-3. TBLM: Traverse center measurement (on/off) TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when 1. - 93 - CXD3017Q $39 (preset: $390000) D15 D14 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 DAC SD6 When $3A command SVDA = 0 DAC: Serial data readout DAC mode setting. When 0, serial data cannot be read out. (default) When 1, serial data can be read out. SD6 to SD0: These bits select the serial readout data. D14 SD6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 Coefficient RAM data Data RAM data 1 0 1 0 0 1 0 1 1 0 1 0 RF AVRG register RFDC input signal FCS Bias register TRVSC register DFCT count VC AVRG register FE AVRG register TE AVRG register RFDC (Bottom) RFDC (Peak) RFDC (Peak - Bottom) FE input signal TE input signal SE input signal VC input signal Readout data Readout data length 8 bits 16 bits 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits : don't care Note) When $3A SVDA is changed, select the readout data again. Coefficient RAM address Data RAM address 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 - 94 - CXD3017Q When $3A command SVDA = 1 DAC: This command selects whether to set readout data for the left or right channel. When 0, right channel readout data is selected. (default) When 1, left channel readout data is selected. SD6 to SD0: These bits select the data to be output from the left or right channel. D14 SD6 0 0 0 0 0 0 1 2 0 0 0 0 0 0 D13 SD5 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 Data RAM data 1 0 1 0 1 0 1 0 RF AVRG register RFDC input signal FCS Bias register TRVSC register VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal Readout data Readout data length 16 bits 8 bits 8 bits 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits Data RAM address 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 : don't care 1 Right channel preset 2 Left channel preset Note) Coefficient RAM data cannot be output from the audio DAC side. Do not output RFDC (peak, bottom, peak-bottom) or the DFCT count from the audio DAC side. When $3A SVDA is changed, select the readout data again. The DFCT count counts the number of times the DFCT signal rises while $3994 is set. Readout outputs the DFCT count at that time. - 95 - CXD3017Q $3A (preset: $3A0000) D15 0 FBON: D14 FBON D13 0 D12 0 D11 0 D10 0 D9 FIFZC D8 0 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 FPS1 FPS0 TPS1 TPS0 SVDA FBIAS (focus bias) register operation setting. FBON 0 1 Processing FBIAS (focus bias) register addition off. FBIAS (focus bias) register addition on. This selects the FZC slice level setting command. When 0, the FZC slice level is determined by the $37 FZSH and FZSL setting values. (default) When 1, the FZC slice level is determined by the $3F8 FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values. This allows more detailed setting and the addition of hysteresis compared to the $37 FZSH and FZSL setting. FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block. These are effective for increasing the overall gain in order to widen the servo band, etc. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. FPS1 0 0 1 1 FPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB TPS1 0 0 1 1 TPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB : preset SVDA: This allows the data set by the $39 command to be output through the audio DAC. When 0, audio is output. (default) When 1, the data set by the $39 command is output. FIFZC: - 96 - CXD3017Q $3B (preset: $3B E0 50) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 x VDD/2, VDD = supply voltage) RFDC input conversion SFOX 0 0 0 0 1 1 1 1 SFO2 0 0 1 1 0 0 1 1 SFO1 0 1 0 1 0 1 0 1 Slice level 16/256 x VDD/2 20/256 x VDD/2 24/256 x VDD/2 28/256 x VDD/2 32/256 x VDD/2 40/256 x VDD/2 48/256 x VDD/2 56/256 x VDD/2 : preset SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 x VDD) RFDC input conversion SDF2 0 0 1 1 SDF1 0 1 0 1 Slice level 0.0156 x VDD 0.0234 x VDD 0.0313 x VDD 0.0391 x VDD : preset, VDD: supply voltage MAX2, MAX1: DFCT maximum time (MCK = 128Fs) Default value: 00 (no timer limit) MAX2 0 0 1 1 MAX1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36 2.72 : preset - 97 - CXD3017Q Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when 1. D2V2, D2V1: Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 x VDD/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D2V2 0 0 1 1 D2V1 0 1 0 1 Count-down speed [V/ms] 0.0431 x VDD 0.0861 x VDD 0.172 x VDD 0.344 x VDD [kHz] 22.05 44.1 88.2 176.4 BTF: : preset, VDD: supply voltage D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (0.688 x VDD/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D1V2 0 0 1 1 D1V1 0 1 0 1 Count-down speed [V/ms] 0.344 x VDD 0.688 x VDD 1.38 x VDD 2.75 x VDD [kHz] 176.4 352.8 705.6 1411.2 : preset, VDD: supply voltage - 98 - CXD3017Q $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 BTS1 BTS0 MRC1 MRC0 COSS, COTS: These select the TZC signal used when generating the COUT signal. COSS 1 0 0 COTS -- 0 1 TZC STZC HPTZC DTZC : preset, --: don't care STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See 4-13. CETZ: Normally, the input from the TE pin enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When 0, the TZC signal is generated by using the signal input to the TE pin. When 1, the TZC signal is generated by using the signal input to the CE pin. When 0, the signal input to the TE pin is input to the TRK servo filter. When 1, the signal input to the CE pin is input to the TRK servo filter. CETF: These commands output the TZC signal. COT2, COT1: The COUT signal is replaced by the TZC signal. Concretely, the TZC signal is output from the COUT pin and the TZC signal is used for auto sequence instead of the COUT signal. COT2 1 0 0 COT1 -- 1 0 COUT pin output STZC HPTZC COUT MOT2: : preset, --: don't care The MIRR signal is replaced by the STZC signal. Concretely, the STZC signal is output from the MIRR pin and the STZC signal is used for generating the COUT signal instead of the MIRR signal. These commands set the MIRR signal generation circuit. BTS1, BTS0: These set the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. These bits are valid only when BTF of $3B is 0. MRC1, MRC0: These set the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in 4-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. These bits set that time. The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R. BTS1 BTS0 0 0 1 1 0 1 0 1 Number of count-up steps per cycle 1 2 4 8 MRC1 MRC0 0 0 1 1 0 1 0 1 Setting time [s] 5.669 11.338 22.675 45.351 : preset (when MCK = 128Fs) - 99 - CXD3017Q $3D (preset: $3D 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 SFID: SFSK: THID: THSK: ABEF: TLD0 to 2: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input. Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. See "4-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands. The focus error (FE) and tracking error (TE) can be generated internally. When 0, the FE and TE signal input mode results. Input each error signal through the FE and TE pins. (default) When 1, the FE and TE signal generation mode results and the FE and TE signals are generated internally. These turn on and off SLD filter correction independently of the TRK filter. See $38 (TLC0 to TLC2) and Fig. 4-3. TLC2 0 1 TLD2 -- 0 1 Traverse center correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC1 0 1 TLD1 -- 0 1 Tracking zero level correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC0 0 1 TLD0 -- 0 1 VC level correction TRK filter OFF ON ON SLD filter OFF ON OFF : preset, --: don't care - 100 - CXD3017Q * Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD3017Q outputs servo drives which have the reversed phase of input errors. Negative input coefficient TE K19 TRK filter Positive output coefficient K22 Negative input coefficient SE K00 SLD filter Positive output coefficient K05 Positive input coefficient TRK Hold K40 TRK Hold filter Positive output coefficient K45 When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so the SLD input coefficient (K00) sign must be inverted. (For example, inverting the sign for coefficient K00: E0h results in 20h.) For the same reason, when THID = 1, the TRK hold input coefficient (K40) sign must be inverted. Negative input coefficient TE K19 TRK filter MOD Positive output coefficient K22 Positive input coefficient SE K00 SLD filter Positive output coefficient K05 Negative input coefficient TRK Hold K40 TRK Hold filter Positive output coefficient K45 For TRK servo gain normal See 4-20. Filter Composition". - 101 - CXD3017Q $3E (preset: $3E 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 0 D4 D3 D2 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD LKIN COIN MDFI MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when 1; default is 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when 1; default is 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when 1; default is 0. Generally, the advance amount of the phase increases by partially setting the FCS servo thirdstage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when 1; default is 0. Generally, the advance amount of the phase increases by partially setting the TRK servo thirdstage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See "4-20 Filter Composition" at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when 1; default is 0 When 0, the internally generated LOCK signal is output to the LOCK pin. (default) When 1, the LOCK signal can be input from an external source to the LOCK pin. When 0, the internally generated COUT signal is output to the COUT pin. (default) When 1, the COUT signal can be input from an external source to the COUT pin. TLCD: LKIN: COIN: The MIRR, DFCT and FOK signals can also be input from an external source. MDFI: When 0, the MIRR, DFCT and FOK signals are generated internally. (default) When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. MIRI: When 0, the MIRR signal is generated internally. (default) When 1, the MIRR signal can be input from an external source through the MIRR pin. MDFI 0 0 1 MIRI 0 1 -- MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. : preset, --: don't care XT1D: The input to the servo master clock is used without being frequency-divided by setting XT1D to 1. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. - 102 - CXD3017Q $3F (preset: $3F 00 10) D15 0 AGG4: D14 D13 D12 D11 D10 D9 D8 D7 0 D6 D5 D4 1 D3 SRO1 D2 0 D1 D0 AGG4 XT4D XT2D AGSD DRR2 DRR1 DRR0 ASFG FTQ AGHF ASOT This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. Sin wave amplitude AGG4 AGGF AGGT 0 0 1 -- -- 0 1 0 1 1 -- -- 0 1 0 1 0 1 FE input conversion 1/32 x VDD/2 1/16 x VDD/2 -- -- TE input conversion -- -- 1/16 x VDD/2 1/8 x VDD/2 1/64 x VDD/2 1/32 x VDD/2 1/16 x VDD/2 1/8 x VDD/2 : preset, --: don't care See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. XT4D, XT2D: MCK (digital servo master clock) frequency division ratio setting This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated. See the description of $3E for XT1D. Also, see "4-2. Digital Servo Block Master Clock (MCK)". XT1D 0 1 0 0 XT2D 0 -- 1 0 XT4D 0 -- -- 1 Frequency division ratio According to XTSL 1/1 1/2 1/4 : preset, --: don't care AGSD: This command is used to determine whether the result of the tracking auto gain adjustment is reflected on the sled. See 4-6 for the auto gain adjustment. When AGSD = 0, the result of the tracking auto gain adjustment is reflected on the sled. In other words, the coefficient K07 = K23. (preset) When AGSD = 1, the result of the tracking auto gain adjustment is not reflected on the sled. In other words, the coefficient K07 is not affected by K23. - 103 - CXD3017Q DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when 1 (on) respectively; default is 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50s or more. ASFG: When vibration detection is performed during anti-shock circuit operation, the FCS servo filter is forcibly set to gain normal status. On when 1; default is 0 FTQ: The slope of the output during focus search is 1/4 the conventional output slope. On when 1; default is 0 SRO1: This command is used to continuously externally output various data inside the digital servo block which have been specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.) Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting this command to 1. SRO1 = 1 SOCK XOLT SOUT AGHF: ASOT: Output from LMUT pin. Output from WFCK pin. Output from RMUT pin. This halves the frequency of the internally generated sine wave during AGC. The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when 1; default is 0. Vibration detection when a high signal is output for the anti-shock signal output. - 104 - CXD3017Q $3F8 (preset: $3F8800) D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SYG3 SYG2 SYG1 SYG0 FIFZB3 FIFZB2 FIFZB1 FIFZB0 FIFZA3 FIFZA2 FIFZA1 FIFZA0 SYG3 to SYG0: These simultaneously set the focus drive, tracking drive and sled drive output gains. See the $CX commands for the spindle drive output gain setting. SYG3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SYG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SYG1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SYG0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (- dB) 0.125 (-18.1dB) 0.250 (-12.0dB) 0.375 (-8.5dB) 0.500 (-6.0dB) 0.625 (-4.1dB) 0.750 (-2.5dB) 0.875 (-1.2dB) 1.000 (0.0dB) 1.125 (+1.0dB) 1.250 (+1.9dB) 1.375 (+2.8dB) 1.500 (+3.5dB) 1.625 (+4.2dB) 1.750 (+4.9dB) 1.875 (+5.5dB) : preset FIFZB3 to FIFZB0: This sets the slice level at which FZC changes from high to low. FIFZA3 to FIFZA0: This sets the slice level at which FZC changes from low to high. The FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values are valid only when $3A FIFZC is 1. Set so that the FIFZB3 to FIFZB0 FIFZA3 to FIFZA0. Hysteresis can be added to the slice level by setting FIFZB3 to FIFZB0 < FIFZA3 to FIFZA0. FZC slice level = FIFZB3 to FIFZB0 or FIFZA3 to FIFZA0 setting value x 0.5 x VDD [V] 32 GAIN - 105 - CXD3017Q Description of Data Readout 64 SOCK (5.6448MHz) XOLT (88.2kHz) MSB 8 bits data MSB SOUT MSB 16 bits data 9 bits data LSB LSB LSB ... 32 ... 16 8 1 16-bit register for serial/parallel conversion SOUT LSB 16-bit register for latch LSB To the 7-segment LED . . . . . To the 7-segment LED . MSB SOCK CLK CLK MSB Data is connected to the 7-segment LED by 4-bits at a time. This enables Hex display using four 7-segment LEDs. XOLT SOUT Serial data input D/A SOCK XOLT Analog output Offset adjustment, gain adjustment To an oscilloscope, etc. Clock input Latch enable input Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. - 106 - CXD3017Q 4-19. List of Servo Filter Coefficients Fix indicates that normal preset values should be used. - 107 - CXD3017Q - 108 - 4-20. Filter Composition The internal filter composition is shown below. K: Coefficient RAM address, M: Data RAM address FCS Servo Gain Normal fs = 88.2kHz M1F K0F M03 M05 M06 K11 K13 Z-1 K10 M07 Z-1 K0C 2-7 K0B K0D Note) Set the MSB bit of the K0B and K0D coefficients to 0. 2-7 27 K0E Z-1 Z-1 K08 K09 K0A M04 To FCS Hold K0F FCS AUTO Gain To FCS Hold M1E FCS Hold Reg2 DFCT FCS In Reg 2-1 K06 AGFON Sin ROM K06 FCS Servo Gain Down fs = 88.2kHz M1F K2B M03 M05 Z-1 K26 K28 2-7 K27 K29 2-7 K2A Z-1 K24 K25 Z-1 M04 To FCS Hold K2B To FCS Hold M06 Z-1 K2C K2D M1E FSC AUTO Gain M07 K13 - 109 - Note) Set the MSB bit of the K27 and K29 coefficients to 0. FPS1, 0 BK3 Z-1 BK1 Z-1 BK2 BK6 Z-1 BK4 FCS Hold Reg2 DFCT FCS In Reg 2-1 K06 PWM Z-1 FCS SRCH BK5 CXD3017Q TRK Servo Gain Normal fs = 88.2kHz To SLD Servo, TRK Hold M0B M0D M0E K22 K23 Z-1 K21 M0F Z-1 K1E 2-7 K1D K1F Note) Set the MSB bit of the K1D and K1F coefficients to 0. 2-7 K20 Z-1 K1A K1B K1C Z-1 M0C TRK AUTO Gain TRK Hold Reg DFCT TRK In Reg 2-1 K19 AGTON Sin ROM K19 TRK Servo Gain Up1 fs = 88.2kHz TRK AUTO Gain M0B M0E K3E M0F K23 Z-1 K3D Z-1 K1A K1B K3C Z-1 M0C 27 TRK Hold Reg DFCT TRK In Reg 2-1 K19 - 110 - To SLD Servo, TRK Hold M0B M0D Z-1 K3A 2-7 2 K3B K39 -7 TRK Servo Gain Up2 fs = 88.2kHz TRK AUTO Gain M0E Z-1 K3D K3E M0F K23 TRK Hold Reg M0C Z-1 K37 K3C K38 DFCT TRK In Reg Z-1 K36 2-1 K19 Note) Set the MSB bit of the K39 and K3B coefficients to 0. TPS1, 0 BK3 Z-1 BK1 BK2 Z-1 BK6 Z-1 BK4 Z-1 TRK JMP BK5 BK7 BK8 BK9 Z-1 Z-1 PWM CXD3017Q FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0) M1F K0F M03 M04 M05 K11 K13 Z-1 K0C 2 2 K0D 27 K0E K09 K0B -7 -7 M1E K0F M06 Z-1 K10 2 -7 FCS Hold Reg 2 M07 DFCT To FCS Hold To FCS Hold FCS AUTO Gain FCS In Reg Z-1 7FH K0A 2 K08 -7 2-1 K06 AGFON 81H 2 -7 Z-1 80H Sin ROM K06 Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09 and K0E coefficients during quasi double accuracy to 0. FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0) K2B M03 M06 K2D Z-1 K2C 2-7 K29 K2A M07 Z-1 7FH K26 K28 2-7 K25 K27 2-7 2-7 K24 2-7 80H Z-1 M04 M05 K13 M1F To FCS Hold K2B To FCS Hold FCS AUTO Gain M1E FCS Hold Reg 2 DFCT FCS In Reg 81H 2-1 K06 Z-1 - 111 - FPS1, 0 BK3 Z-1 BK1 Z-1 BK2 BK6 Z-1 BK4 BK5 Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0. 81h, 7Fh and 80h are each Hex display 8-bit fixed values when set to quasi double accuracy. Z-1 FCS SRCH PWM CXD3017Q TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0) TRK AUTO Gain M0C M0D M0E K22 K23 Z-1 80H K21 2-7 K1F K20 M0F Z-1 K1C K1E 2-7 K1B K1D 2-7 Z-1 7FH 2-7 2-7 TRK Hold Reg DFCT TRK In Reg 2-1 M0B K19 AGTON Z-1 Sin ROM K19 81H K1A Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. TRK Servo gain up1; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK AUTO Gain M0C M0E K3E Z-1 7FH K3D 2-7 K1B K3C 2-7 2-7 80H Z-1 M0F K23 27 TRK Hold Reg DFCT 2-1 M0B TRK In Reg K19 Z-1 81H K1A - 112 - M0C M0D Z-1 K38 K3A 2-7 K37 K39 K3B K3C 2-7 2-7 80H Z-1 Z-1 7FH 2-7 2-7 M0E K3E Z-1 K3D M0F TPS1, 0 BK3 Z-1 BK1 Z-1 BK2 BK6 Z-1 BK4 Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. TRK Servo gain up2; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK AUTO Gain K23 TRK Hold Reg DFCT TRK In Reg 2-1 K19 M0B Z-1 81H K36 Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. 81h, 7Fh and 80h are each Hex display 8-bit fixed values when set to quasi double accuracy. BK9 Z-1 TRK JMP BK5 Z-1 BK7 BK8 Z-1 PWM CXD3017Q CXD3017Q SLD Servo fs = 345Hz TRK SERVO FILTER Second-stage output K30 M0D 2-1 SFID K00 Z-1 K01 2-7 K02 2-7 K04 Z-1 SLD MOV K03 SFSK (only when TGup2 is used.) M00 SLD In Reg M01 K05 TRK AUTO Gain M02 27 K07 PWM Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz FCS In Reg TRK In Reg Sin ROM 2-1 AGFON 2-1 AGTON AGFON M08 Z-1 K14 K15 M09 Z-1 Slice TZC Reg M0A Z-1 K17 AUTO Gain Reg Slice - 113 - CXD3017Q Anti Shock fs = 88.2kHz 2-1 TRK In Reg K12 M08 Z-1 M09 Z-1 K31 K16 2-7 M0A Z-1 K33 K35 Comp Anti Shock Reg K34 Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz 2-1 VC, TE, FE, RFDC 2-7 M08 Z-1 AVRG Reg TRK Hold fs = 345Hz TRK SERVO FILTER Second-stage output K46 M0D 2-1 THID K40 Z-1 K41 2-7 K42 2-7 K44 Z-1 K43 THSK (only when TGup2 is used) M18 SLD In Reg M19 K45 TRK Hold Reg Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz FCS SERVO FILTER First-stage output M04 DFIS ($3E) K2B M1F K2B when using the FCS Gain Down filter M10 Z-1 K49 2-7 K4A 2-7 K4C M11 Z-1 K4B M12 FCS Hold Reg 2 M05 FCS SERVO FILTER Second-stage output K0F K48 M1E K4D Note) Set the MSB bit of the K4A and K4C coefficients to 0. - 114 - CXD3017Q 4-21. TRACKING and FOCUS Frequency Response TRACKING frequency response 40 NORMAL GAIN UP 30 90 180 G - Gain [dB] 20 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1k -180 20k When using the preset coefficients with the boost function off. FOCUS frequency response 40 NORMAL GAIN DOWN 90 20 180 30 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1k -180 20k When using the preset coefficients with the boost function off. - 115 - - Phase [degree] G - Gain [dB] - Phase [degree] 5. Application Circuit 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DOUT VDD VSS PCO FILI FILO BIAS ASYI CLTV RFAC ASYO IGEN ADIO DOUT LRCK FE 39 VC 38 XTSL 37 TES1 36 TEST 35 VSS 34 FRDR 33 FFDR 32 TRDR 31 TFDR 30 SRDR 29 SFDR 28 SSTP 27 MDP 26 LOCK 25 FOK 24 DFCT 23 MIRR 22 COUT 21 DFCT MIRR COUT LOCK Driver Circuit AVDD3 AVSS3 AVDD0 AVSS0 RFDC CE TE SE 40 61 LRCK PCMD 62 PCMD BCK 63 BCK FG TD TG FD LDON Vcc GND RFO FZC FE TE CE VC EMPH 64 EMPH 65 XVDD 66 XTAI 67 XTAO 68 XVSS 69 AVDD1 70 AOUT1 71 AIN1 72 LOUT1 SYSM VDD XRST SCLK WFCK XUGF SQCK SENS XLON SQSO CLOK SPOB XLAT SPOA DATA 1 3 4 7 8 2 5 6 9 10 11 12 13 14 15 16 17 18 19 20 ATSK XLON XUGF XPCK GFS SQSO SQCK XRST MUTE DATA XLAT CLOK SENS SCLK GFS SCOR FOK LDON VDD GND WFCK XPCK C2PO C2PO SCOR - 116 - 73 AVSS1 74 AVSS2 +5V SSTP SLED SPDL GND 75 LOUT2 76 AIN2 77 AOUT2 78 AVDD2 RMUT 79 RMUT LMUT 80 LMUT CXD3017Q Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD3017Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1 41 40 16.0 0.4 + 0.4 14.0 - 0.1 60 61 80 1 0.65 20 0.24 21 + 0.15 0.1 - 0.1 M 0 to 10 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 QFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g - 117 - 0.5 0.2 + 0.15 0.3 - 0.1 (15.0) |
Price & Availability of CXD3017Q
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |